The present disclosure relates to the design and manufacturing of integrated circuits and, more specifically, to the use of databases, graphs, machine learning, search algorithms, etc., for optimizing complex multi-dimensional integrated circuit design and manufacturing configurations, for example, to improve design and manufacturing objectives, such as manufacturing yield.
By way of example, integrated circuit manufacturing yield may be the result of a complex multi-dimensional set of interactions among process, materials, tool settings, design variations, design complexity and other random events. The rapid pace of the semiconductor industry and the ever-increasing cost and competitive pressures on the integrated circuit fabrication plant (fab) contributes to the challenge of improving yield.
Traditional yield improvement efforts typically address problems after they have occurred. For example, engineers may observe problems in simulation, through physical defects on the integrated circuit devices, or in electrical failures of devices. High frequency problems may be prioritized the cause of each problem may be isolated through hypothetical analysis. Once a hypothetical cause is identified, the integrated circuit design or manufacturing process may be changed to attempt to remove the cause of the problem or to add a safety margin to mitigate the impact of the problem.
Subsequent observations may be used to determine whether the changes demonstrate an improvement over the prior method.
Any changes that demonstrate a significant reduction in observed problems may be preserved, and any changes that demonstrate an increase in observed problems may be discarded. Disadvantageously, some changes demonstrate a reduction in some problems, but also introduce new problems. This ambiguous result is a consequence of complex multi-factorial interactions in design and manufacturing. Consequently, the ramp up in improvement of yield is a laborious process that takes place over several years. Furthermore, the difficulty in execution of this process continues to increase as both the integrated circuit designs, and their fabrication process increase in complexity. This is evidenced in the industry by increased design and manufacturing cost per technology node, the consolidation of integrated circuit design and manufacturing companies, and the slowing of the pace of introduction of new technology nodes.
Restricted design rules are often used in an attempt to eliminate pre-identified, yield-limiting structures. However, even these restricted design rules can allow a number of yield-limiting patterns to enter the fab, and additional defects may be discovered after problems or failures are caused. In such a manual improvement process, the cycle of learning is repeated, new yield-limiters are identified and eliminated, and eventually the yield may increase incrementally.